Modern integrated circuits (ICs), which can be classified as digital, analog, or mixed signal, can provide extremely complex functionality. A single IC can include millions or billions transistors, each of which can switch on and off at billions of times each second, causing minute amounts of current to propagate through various pathways within the ICs. In the design phase of an IC, a designer specifies a set of target process parameters, such as gate length, electron mobility, and voltage threshold, for each transistor on an IC prior to manufacturing.
Due to the extremely small feature sizes and complex functionality involved, manufacturing such ICs can take several months from start to finish in many instances. A fabrication facility attempts to manufacture each transistor so that each transistor has precisely the target process parameters specified by the designer. Thus, when the final IC is manufactured, the aim is for the manufactured IC to meet the performance metrics envisioned by the designer. However, due to small, unpredictable variations in the manufacturing environment, transistors on a given IC and across multiple ICs will exhibit variations in performance. Process corners are used to characterize these manufacturing variations. Process corners represent different conditions of manufacturing variations within which a circuit functions correctly.
FIG. 1 shows an example process corner chart 100 for a large number of manufactured devices with manufacturing variations there between. In particular, along the x-axis, FIG. 1 illustrates current variation (In) for identically specified NMOS devices having a first target set of conditions (i.e., a predetermined gate-source voltage (VGSN), drain-source voltage (VDSN), gate width (WN), and gate length (LN)). Along the y-axis, the chart illustrates current variation (Ip) for identically specified PMOS devices having a second target set of conditions (i.e., a predetermined VGSP, VDSP, WP, and LP). Because of manufacturing variation, the NMOS and PMOS devices each have slightly different currents In, Ip that fall within a polygon 102 bounded by four process corners. Some ICs exhibit the specified target behavior (referred to as “nominal” or “typical-typical” devices) and are represented by point 104. Other devices are classified as being fast/fast (represented by corner 106), slow/slow (represented by corner 108), or “skewed”. “Skewed” corners can be fast/slow (represented by corner 110) or slow/fast (represented by corner 112). Thus, a single, randomly selected device formed by this process may run slower or faster than specified by a designer, depending on whether its manufactured devices statistically fall nearer a fast process corner or a slow process corner. If not accurately accounted for, this manufacturing variation among devices and ICs can potentially reduce the overall yield, and correspondingly reduce the number of viable ICs produced over time.
To account for these process corners prior to submitting an IC design to the fabrication facility, design engineers simulate each IC, for example in a Simulation Program with Integrated Circuit Emphasis (SPICE) simulation. To predict possible manufacturing outcomes, these SPICE simulations use a technique referred to as Monte-Carlo modeling, where the IC is simulated a large number of times with different, randomly-chosen device parameters selected for each simulation. Each simulation provides a different point on a process corner chart. Thus, some simulated device parameters result in fast/fast or slow/slow devices or ICs, other simulated device parameters result in skewed devices or ICs, while still other simulated device parameters result in devices or ICs falling elsewhere within the polygonal bounds of process corners provided by a fabrication facility.
Randomly varying the device parameters in these Monte Carlo simulations models the vast number of possible manufacturing variations that can occur when the device is actually manufactured. Designers can then identify worst case scenarios where, although the device parameters fall within established process corners, the proposed design still fails to meet its design specifications. For example, if a design specification calls for an IC to be stable for all clock frequencies between 1.1 GHz and 1.3 GHz over a temperature range of −10° C. to 80° C. (and process corners allow MOSFET voltage thresholds and electron mobility to each vary by as much as 10% while remaining within the process corners), simulations might show the IC is expected to fail for a worst-case scenario at the 1.3 GHz clock frequency at 80° C. when MOSFET voltage thresholds are 10% higher than a target voltage threshold and when MOSFET electron mobility is 10% lower than a target electron mobility. If a worst case failure scenario is identified, the designers can tune the proposed design to make it more robust to stay within the design specifications.
Unfortunately, carrying out the vast number of Monte Carlo simulations required to identify whether an IC might fail to meet its design specifications can take a significant amount of time and computing resources.